Pipelined architecture for real-time cost-optimized extraction of visual primitives based on FPGAs

Abstract

This paper presents an architecture for the extraction of visual primitives on chip: energy, orientation, disparity, and optical flow. This cost-optimized architecture processes in real time high-resolution images for real-life applications. In fact, we present a versatile architecture that may be customized for different performance requirements depending on the target application. In this case, dedicated hardware and its potential on-chip implementation on FPGA devices become an efficient solution. We have developed a multi-scale approach for the computation of the gradient-based primitives. Gradient-based methods are very popular in the literature because they provide a very competitive accuracy vs. efficiency trade-off. The hardware implementation of the system is performed using superscalar fine-grain pipelines to exploit the maximum degree of parallelism provided by the FPGA. The system reaches 350 and 270 VGA frames per second (fps) for the disparity and optical flow computations respectively in their mono-scale version and up to 32 fps for the multi-scale scheme extracting all the described features in parallel. In this work we also analyze the performance in accuracy and hardware resources of the proposed implementation.

Publication
Digital Signal Processing
Francisco Barranco
Francisco Barranco
Associate Professor

Associate Professor at the Department of Computer Engineering, Automation and Robotics, Principal Investigator at the Applied Computational Neuroscience Group and the Computer Vision and Robotics Lab of the University of Granada.

Eduardo Ros
Eduardo Ros
Full Professor

Full professor in computer architecture, principal investigator at the Computational Neuroscience and Neurorobotics Lab and principal investigator of the VALERIA lab of the University of Granada.