We present a model and a hardware architecture for the computation of bottom-up inherent visual attention for FPGA. The bottom-up inherent attention is generated including local energy, local orientation maps, and red-green and blue-yellow color opponencies. In this work, we describe the simplifications to parallelize and embed the model without significant accuracy loss. We also include feedback loops to adapt the weights of the features, depending on the target application.
Electronics, Circuits and Systems (ICECS), 2012 19th IEEE International Conference on
Full professor in computer architecture, principal investigator at the Computational Neuroscience and Neurorobotics Lab and principal investigator of the VALERIA lab of the University of Granada.
Associate Professor at the Department of Computer Engineering, Automation and Robotics and Principal Investigator at the Applied Computational Neuroscience Group.