Parallel architecture for hierarchical optical flow estimation based on FPGA

Francisco Barranco, M. Tomasi, J. Díaz, M. Vanegas, Eduardo Ros
August 2012
Journal

Abstract

The proposed work presents a highly parallel architecture for motion estimation. Our system implements the well-known Lucas and Kanade algorithm with the multi-scale extension for the computation of large motion estimations in a dedicated device field-programmable gate array (FPGA). Our system achieves 270 frames per second for a 640× 480 resolution in the best case of the mono-scale implementation and 32 frames per second for the multi-scale one, fulfilling the requirements for a real-time system. We describe the system architecture, address the evaluation of the accuracy with well-known benchmark sequences (including a comparative study), and show the main hardware resources used.

Type
Journal article
Publication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Francisco Barranco
Francisco Barranco
Associate Professor

Associate Professor at the Department of Computer Engineering, Automation and Robotics, Principal Investigator at the Applied Computational Neuroscience Group and the Computer Vision and Robotics Lab of the University of Granada.

Eduardo Ros
Eduardo Ros
Full Professor

Full professor in computer architecture, principal investigator at the Computational Neuroscience and Neurorobotics Lab and principal investigator of the VALERIA lab of the University of Granada.